1. Field
Various embodiments of the present invention relate to a semiconductor device, and, more particularly, to a semiconductor device including a through chip via.
2. Description of the Related Art
In general, technology for packaging semiconductor integrated circuits has developed to satisfy the demands of miniaturization, mounting reliability, and high performance. Recently, various technologies for stacked packages have been developed in an attempt to satisfy these demands. An example of a stacked package can be seen, in 3-dimensional (3D) semiconductor devices having multiple chips that are stacked in a single package, allowing an increase in the integration degree thereof. In this example, the stacked chips are electrically coupled through through-chip vias, for example, through-silicon vias (TSVs).
A TSV is formed through the semiconductor chips. The TSV may be formed as follows. First, a through-hole may be bored in the semiconductor chip, and a silicon-based insulating layer (e.g., a silicon oxide layer) may be formed on the inner circumference of the through-hole. Then, the through-hole may be filled with a conductive material to form a TSV capable of transmitting an electrical signal.
However, when data is transmitted through the TSV during a write or read operation of the semiconductor chip, current consumption may increase due to high capacitance in the TSV at low-voltages and/or high-speed states, during signaling of data. Thus, when multiple TSVs are driven, power consumption may momentarily increase.